Certain memory cells, e.g., flash memory cells, include at least one floating gate programmed and erased through one or more program/erase gates, word lines, or other conductive element(s). Some memory cells use a common program/erase gate extending over a floating gate to both program and erase the cell. In some implementations, the floating gate is formed by a Poly1 layer, while the program/erase gate is formed by a Poly2 layer that partially overlaps the underlying Poly1 floating gate in the lateral direction. For some memory cells, the manufacturing process includes a floating gate thermal oxidation process that forms a football-shaped oxide over the Poly1 floating gate, as discussed below.
FIG. 1 illustrates a partial cross-sectional view of an example memory cell 10A, e.g., a flash memory cell, including a Poly1 floating gate 14 and an overlying football-shaped oxide region (“football oxide”) 16 formed over a substrate 12, and a Poly2 gate 18 (e.g., a word line, erase gate, or common program/erase gate) extending partially over the floating gate 14. The football oxide 16 is formed over the floating gate 14 by a thermal oxidation process on floating gate 14, which defines upwardly-pointing tips 15 at the edges of floating gate 14. One or more of these FG tips 15 may define a conductive coupling to adjacent program/erase gates. For example, the FG tip 15 on the right side of FG 14 shown in FIG. 1 may define a conductive coupling to the adjacent Poly2 gate 18.
After forming the floating gate 14 and football oxide 16, a source dopant implant may be performed, which is self-aligned by the lateral edge of the floating gate 14, followed by an anneal process that diffuses the source dopant outwardly such that the resulting source region extends partially under the floating gate 14, as shown in FIG. 1. However, during the source dopant implant, a portion of the dopant may penetrate through the football oxide 16 and into the underlying floating gate 14, which may result in a dulling or blunting of one or more floating gate tips 15, e.g., after subsequent oxidation steps (wherein the dopant absorbed in the floating gate 14 promotes oxidation of the floating gate tips 15). This dulling or blunting of the floating gate tip(s) 15 may decrease the efficiency of erase and/or program operations of the memory cell 10A.
FIGS. 2A and 2B illustrate example cross-sections taken at selected times during a conventional manufacturing process for a conventional flash memory cell including multiple floating gates. As shown in FIG. 2A, a Poly1 layer 30 may be deposited over a silicon substrate. A nitride layer may then be deposited and patterned using known techniques to form a hard mask 32. As shown in FIG. 2B, a floating gate oxidation process may then be performed, which forms a football oxide 16 over areas of the Poly1 layer 30 exposed through the nitride mask 32 (which subsequently defines the floating gates 14). The nitride mask 32 may subsequently be removed, followed by a plasma etch to remove portions of the Poly1 layer 30 uncovered by each football oxide 16, which defines the lateral extent of each floating gate 14. This may be followed by a source implant and/or formation of a Poly2 layer (e.g., to form a word line, erase gate, coupling gate, etc.), depending on the particular implementation.
FIG. 3 illustrates an example mirrored memory cell 10B (e.g., a SuperFlash ESF1 cell) including two spaced-apart floating gates 14, a word line 20 formed over each floating gate 14, a source region formed between and extending laterally below the two floating gates, and a bit line 18 on each side of the cell, each of which may be contacted by a bit line contact (not shown). In this cell, the source may be formed after forming the word lines 20, e.g., by an HVII implant and subsequent diffusion process. During the source implant, floating gate tips 15A that form conductive couplings with respective word lines 20 are protected from the source dopant by the overlying word lines 20. The interior floating gate tips 15B are relatively unprotected by the football oxides 16 and may thus become dulled or blunted by the dopant and subsequent oxidation, as discussed above. However, interior floating gate tips 15B are not used for conductive coupling and thus the dulling/blunting of floating gate tips 15B generally does not affect the operation of the cell.
Other types of cells include a gate or other operative structure formed over the source region that utilize the interior floating gate tips 15B for conductive coupling to the floating gates 14, e.g., the cell shown in FIG. 4.
FIG. 4 illustrates another example mirrored memory cell 10B (e.g., a SuperFlash ESF1+ cell) including two spaced-apart floating gates 14, a word line 20 formed over each floating gate 14, and a common erase gate or “coupling gate” 22 formed between and extending over both floating gates 14 (such that the program and erase couplings to each respective floating gate 14 may be decoupled), and a source region formed below the common erase gate. The inclusion of the erase gate may improve the cell shown in FIG. 3, e.g., by providing lower operating voltage and enhanced scalability. The word lines 20 and erase gate 22 may be formed simultaneously from a common poly layer. With this cell structure, implanting the source region before forming the word lines 20 and erase gate 22 may result in dulling/blunting of all floating gate tips 15A and 15B, as the tips may be protected only the by football oxides 16. Alternatively, implanting the source region after forming the word lines 20 and erase gate 22 may require a very high powered implant in order to penetrate through the erase gate 22 and into the substrate 12. Such high powered implant is typically costly and may also result in dulling/blunting of floating gate tips 15A and/or 15B.
One proposed technique to protect the floating gate tips during a source implant performed before forming the word lines and erase gate involves modifying the typical source implant mask so that the implant is spaced slightly away from the floating gate edge(s). However, there are drawbacks to such technique. First, scaling of this type of memory cell is generally limited due to photolithography limitations. For example, the space must be large enough to reliably open for the source implant. Second, the overlay alignment of the source implant mask is often imperfect, which introduces asymmetry into cell pairs.